1. Field of the Invention
The present invention relates to a semiconductor device having a pulse generator circuit and an internal voltage generator circuit, the semiconductor device being capable of adjusting values of a pulse width of the pulse generated by these circuits and a value of an internal voltage. More particularly, the present invention relates to a nonvolatile semiconductor memory that internally generates a reference voltage, a writing voltage, a erasure voltage, and a readout voltage.
2. Description of the Related Art
An NAND type flash memory that is one type of nonvolatile semiconductor memory is announced by literature such as K. Imamiya et. al. xe2x80x9cA 130-mm2 256-Mb NAND Flash with Shallow Trench Isolation Technologyxe2x80x9d, IEEE J. Solid State Circuits, Vol. 34, pp. 1536-1543, November 1999xe2x80x9d or the like.
In such a nonvolatile semiconductor memory, voltage trimming and defective cell redundancy replacement are carried out in a wafer test process.
FIG. 35 is a flowchart showing an outline of a conventional wafer testing process. The operating contents of each process are as follows.
In a DC test, DC checks such as contact check and standby current are made. In Vref (reference voltage) trimming, Wref of each chip on a wafer is monitored, and then, it is computed as to what a trimming value should be determined inn order to correct these to a target value.
Next, Vpgm (writing voltage) initial value trimming is carried out. In a NAND type flash memory, there is employed Incremental Step Pulse Programming Scheme that increments a writing voltage Vpgm from an initial value in a stepwise manner. This method is described in xe2x80x9cK. D. Suh et. al., xe2x80x9cA 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Schemexe2x80x9d, xe2x80x9cISSCC Digest of Technical Papers, pp. 128-129, February 1995xe2x80x9d, for example. In this writing method, it is required to optimize an initial value of Vpgm in order to ensure that a write time (or write loop count) is included within a predetermined time (count). For that purpose, it is required to find a block (good block) that can be written and erased from the inside of a memory cell array. This is because redundancy replacement of a defective cell is not carried out at this step.
If a good block is found, writing is carried in that block while an initial value of Vpgm is changed, and an optimal value is determined.
Subsequently, voltage trimming fuse cutting is carried out. At this step, a wafer is moved to a laser blow unit, and fuse cutting is carried out according to the above Vref trimming and a trimming value determined by Vpgm initial value trimming.
Subsequently, defective column/row detection is carried out. Here, for redundancy replacement, some data patterns are written into a memory cell array, and a defective column/row is detected.
Next, redundancy fuse cutting is carried out. Here, a wafer is moved to a laser flow unit again, and fuse cutting of redundancy replacement is carried out.
In this flowchart, voltage trimming fuse cutting is carried out before detecting a defective column/row because there is a possibility that, if defective column/row detection is carried out in a state in which an internally generated voltage such as Vpgm is shafted, a defect cannot be found.
A testing time at the above described wafer testing step is reflected in chip cost. Therefore, in order to reduce a chip cost, it is required to reduce a test time to the minimum while required wafer testing is carried out.
At the above described wafer test step, there are two factors that a test time is increased. One lies in the existence of a fuse cut step itself. In order to carry out fuse cutting by means of laser blowing, it is required to remove a wafer from a tester, and move the wafer to a laser blow unit. Here, a time overhead is produced. At the above described wafer test step, in particular, it is required to carry out fuse cutting separately twice, thus making the overhead more significant.
The second factor lies in a tester computation time, in order to reduce a test time, commands are assigned to about 100 chips at the same time at the wafer test step, and a tester is used such that an output can be measured at the same time. However, such a tester cannot carry out completely in parallel an operation for computing a trimming value from a monitored voltage or an operation for detecting a defective column row from a readout data pattern. A maximum of 10 chips can be processed in parallel. Therefore, even if data for 100 chips can be acquired at the same time, operational processing for such data must be carried out by being divided by 10 times, and here, a time overhead occurs.
A method for reducing a time for the fuse cutting step of the above two factors is described by the invention relating to application of Japanese Patent Application Publication No. 11-351396 made by the Applicant. The outline is given below.
In a nonvolatile semiconductor memory, a memory cell can store information in a nonvolatile manner. Thus, if a voltage trimming value or redundancy information is stored in a memory cell array, fuse and fuse cutting step can be eliminated. When a nonvolatile semiconductor memory is placed in a normal operation state, although it is required to store the previous trimming value or redundancy information in a predetermined register, the storage operation, i.e., an operation for acquiring information from the inside of a memory cell array, thereby storing the information in a register may be carried out at a time when a power is supplied to a nonvolatile semiconductor memory.
According to an aspect of the present invention, there is provided a semiconductor device comprising:
a bit line;
a plurality of memory cells connected to the bit line; and
a sense amplifier connected to one end of the bit line; and
a defect detector circuit configured to read out data by the sense amplifier while setting a plurality of memory cells connected to the bit line all to a non-selected state, and the other end of the bit line being connected to a predetermined potential via a switch, and an open-circuit defect of the bit line being detected according to a readout data by the sense amplifier.
According to another aspect of the present invention, there is provided a semiconductor device comprising:
a memory cell array in which programmable and erasable nonvolatile memory cells are arranged in column and row directions of a matrix;
an address register that can store an address of a unit of memory cells which are programmed and erased simultaneously in the memory cell array; and
a control circuit that carries out an erase verify operation configured to output a xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d signal according to whether or not all the memory cells targeted for erasing are erased, a write verify operation configured to output the xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d signal according to whether or not all the memory cells targeted for writing are written, and an operation activated upon receipt of a first command, for, when either of results of the erase verify and write verify operations is xe2x80x9cfailxe2x80x9d, changing data of the address register, and when the results are xe2x80x9cpassxe2x80x9d, disabling change of data of the address register.
According to a further aspect of the present invention, there is provided a semiconductor device comprising a register activated by a command input, the register having plural types of test operations configured to output a xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d signal, wherein, if a result of an immediately preceding test that has been carried out of the test operations is xe2x80x9cpassxe2x80x9d, no data is changed, and if the result is xe2x80x9cfailxe2x80x9d, data is set in a predetermined signal state.
According to a further aspect of the present invention, there is provided a semiconductor device having erase verify and write verify functions comprising:
memory cells;
an address register that can store an address of a unit of memory cells which are programmed and erased simultaneously in the memory cell array;
a first register that stores a xe2x80x9cpassxe2x80x9d and xe2x80x9cfailxe2x80x9d result after an erase verify operation;
a second register that stores a xe2x80x9cpassxe2x80x9d and xe2x80x9cfailxe2x80x9d result after a write verify operation;
a third register provided for each erase unit, the third register configured to store a first or second signal state according to whether or not the memory cells in the erase unit are write-erasable or not; and
a control circuit activated upon receipt of a first command input, the control circuit making an operation such that, when at least one of the first register data and second register data is xe2x80x9cfailxe2x80x9d, a third register corresponding to an address selected by the address register is set to a first signal state, and when both of the first register data and second register data are xe2x80x9cpassxe2x80x9d, the third register is set to a second signal state.
According to a further aspect of the present invention, there is provided a semiconductor device comprising:
an internal circuit whose operation or function changes based on data stored in a register; and
a control circuit that repeatedly makes a first operation to carry out a self-judgment test for the internal circuit such that a result of either of xe2x80x9cpass and xe2x80x9cfailxe2x80x9d is outputted and a second operation to carry out a different control for the register according to the xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d result in the self-judgment test, wherein data reflecting the characteristics of each semiconductor device is set to the register.
According to a further aspect of the present invention, there is provided a semiconductor device comprising:
an internal circuit in which an output is trimmed in 2N different schemes by a register capable of holding N-bit data (where N denotes a positive integer); and
a data setting circuit that judges in a first test the output of the internal circuit while the N-bit data is placed in a first state, to determine most significant bit data of the N-bit data; judges, in a kth test (k=2, 3, . . . N), while data from the most significant bit to a (kxe2x88x921)th bit is maintained to a value determined in a first to (kxe2x88x921)th test, the output of the internal circuit with the remaining bit being placed in a predetermined value to determine a kth bit data; and sets data reflecting characteristics of each semiconductor device to the register by the N tests.
According to a further aspect of the present invention, there is provided a semiconductor device comprising:
a memory cell array having a column region and a row region in which memory cells are arranged in column and row directions of a matrix;
a redundancy column region having M redundancy columns for replacement with a defective column in the memory cell array;
M registers configured to store column addresses to be replaced with the redundancy columns, each of the M registers including a latch placed to a first or second signal state according to whether or not a corresponding redundancy column can be used;
a sense amplifier;
a counter that selects the M registers sequentially;
a judgment circuit that makes a judgment on whether or not data of a selected column outputted from the sense amplifier coincides with a predetermined expected value and outputs a xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d signal according to a result of the judgment; and
a control circuit that sets a column address and the counter to a start address, when a defective column in the memory cell array is to be detected; makes, if an output of the judgment circuit is xe2x80x9cpassxe2x80x9d, an increment of the column address, and, if the output of the judgment circuit is xe2x80x9cfailxe2x80x9d, and the latch of the register selected by the counter is placed in the first signal state, stores the column address in the register and thereafter making an increment of the column address and the counter; makes an increment of the counter until the counter has reached a register whose latch is placed in the first signal state, if the output of the judgment circuit is xe2x80x9cfailxe2x80x9d and the latch of the register selected by the counter is placed in the second signal state, thereafter, stores the column address in the register, and thereafter, makes an increment of the column address and the counter, and performs the operations until the counter has reached an end column address.
According to a further aspect of the present invention, there is provided a semiconductor device comprising:
a memory cell array in which programmable and erasable nonvolatile memory cells are arranged in column and row directions of a matrix;
a sense amplifier;
a bit line extending in the column direction, configured to transmit data of the memory cell array to the sense amplifier; and
a column defect detecting circuit that detects a defective column of the memory cell array, without carrying out writing and erasing operation for the memory cells.
According to a further aspect of the present invention, there is provided a method of testing a semiconductor device, the semiconductor device comprising: a memory cell array in which programmable and erasable nonvolatile memory cells are arranged in column and row directions of a matrix; an address register that can store an address of a unit of memory cells which are programmed and erased simultaneously in the memory cell array; and a control circuit that carries out an erase verify operation for outputting a xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d signal according to whether or not all the memory cells targeted for erasing are erased, a write verify operation for outputting the xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d signal according to whether or not all the memory cells targeted for writing are written, and an operation activated upon receipt of a first command, for, when either of results of the erase verify and write verify operations is xe2x80x9cfailxe2x80x9d, changing data of the address register, and when the results are xe2x80x9cpassxe2x80x9d, disabling change of data of the address register, wherein in the method of testing a semiconductor device, series of operations comprising an erasing operation, an erase verify operation, a writing operation, a write verify operation and the first command input are repeated a plurality of times, to find a write-erasable region in a memory cell array.
According to a further aspect of the present invention, there is provided a method of testing a semiconductor device, the semiconductor device comprising a register activated by a command input, the register having plural types of test operations for outputting a xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d, signal, wherein, if a result of an immediately preceding test that has been carried out of the test operations is xe2x80x9cpassxe2x80x9d, no data is changed, and if the result is xe2x80x9cfailxe2x80x9d, data is set in a predetermined signal state, wherein in the method of testing a semiconductor device, plural types of the test operations are carried out, and thereafter, it is judged whether or not the register data is set to a predetermined signal state to judge whether the semiconductor device is normal or defective.
According to a further aspect of the present invention, there is provided a method of testing a semiconductor device integrated on a semiconductor chip, the semiconductor device comprising a memory cell array that comprises nonvolatile memory cells; a first register that stores an address of a defective region in the memory cell array; a plurality of internal voltage generator circuits; and a second register provided corresponding to each of the plurality of internal voltage generator circuits, the second register storing a trimming value for setting an internal voltage value generated by each of the internal voltage generator circuits, the semiconductor device being integrated on a semiconductor chip, the method of testing a semiconductor device, comprising:
resetting the address of the defective region stored in the first register and the trimming value stored in the second register; and
setting the address of the defective region stored in the first register and the trimming value stored in the second register to a value according to a property of each of the semiconductor chips, wherein the testing is carried out without turning a power supply off after the power supply has been turned on.
According to a further aspect of the present invention, there is provided a method of testing a semiconductor device integrated on a semiconductor chip, the semiconductor device comprising an internal circuit in which an operation or function is changed based on data stored in a register, the method of testing a semiconductor device, comprises:
a first operation configured to cause the internal circuit to carry out a self-judgment test such that a result indicating either xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d, is outputted, and
a second operation configured to carry out for the register a control that is different depending on the result of xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d in the self-judgment test, wherein the first operation and second operation are repeated alternately in a predetermined number of times to set for the register data reflecting characteristics of each of the semiconductor chips.
According to a further aspect of the present invention, there is provided a method of testing a semiconductor device, the semiconductor device having an internal circuit in which an output is trimmed in 2N different schemes by a register capable of holding N-bit data (where N denotes a positive integer), the method of testing a semiconductor device comprising:
judging in a first test the output of the internal circuit while the N-bit data is placed in a first state, to determine most significant bit data of the N-bit data;
judging, in a kth test (k=2, 3, . . . N), while data from the most significant bit to a (kxe2x88x921)th bit is maintained to a value determined in a first to (kxe2x88x921)th test, the output of the internal circuit with the remaining bit being placed in a predetermined value to determine a kth bit data; and
setting data reflecting characteristics of each semiconductor device to the register by the N tests.
According to a further aspect of the present invention, there is provided a method of testing a semiconductor device, the semiconductor device comprising a memory cell array in which programmable and erasable nonvolatile memory cells are arranged in column and row directions of a matrix; a sense amplifier; and a bit line extending in the column direction, configured to transmit data of the memory cell array to the sense amplifier, wherein,
the method of testing a semiconductor device, comprises determining whether or not an open-circuit, short-circuit or leak is presented in the bit line and sense amplifier to detect a defective column of the memory cell array, without carrying out writing and erasing operation for the memory cells.
According to a further aspect of the present invention, there is provided a method of detecting and replacing a defective column in a semiconductor device, the semiconductor device comprising a memory cell array having a column region and a row region in which memory cells are arranged in column and row directions of a matrix; a redundancy column region having M redundancy columns for replacement with a defective column in the memory cell array; M registers configured to store column addresses to be replaced with the redundancy columns, each of the M registers including a latch placed to a first or second signal state according to whether or not a corresponding redundancy column can be used; a sense amplifier; a counter that selects the M registers sequentially; and a judgment circuit that makes a judgment on whether or not data of a selected column outputted from the sense amplifier coincides with a predetermined expected value and outputs a xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d signal according to a result of the judgment, wherein,
the method of detecting and replacing a defective column in a semiconductor device comprising:
setting a column address and the counter to a starting address, when a defective column in the memory cell array is to be detected;
making, if an output of the judgment circuit is xe2x80x9cpassxe2x80x9d, an increment of the column address, and, if the output of the judgment circuit is xe2x80x9cfailxe2x80x9d and the latch of the register selected by the counter is placed in the first signal state, storing the column address in the register and thereafter making an increment of the column address and the counter after;
making an increment of the counter until the counter has reached a register whose latch is placed in the first signal state, if the output of the judgment circuit is xe2x80x9cfailxe2x80x9d, and the latch of the register selected by the counter is placed in the second signal state, thereafter, storing the column address in the register, and thereafter, making an increment of the column address and the counter; and
carrying out the above operations until the counter has reached an end column address.